1. Field
The following description relates to a technique of controlling access to a multi-bank memory.
2. Description of the Related Art
A digital signal processor into which a multi-core and a multi-port memory access architecture are adopted reduces memory conflicts by using a multi-bank memory. A multi-bank architecture involves the segmentation of a memory into a plurality of banks using address block based allocation or interleaved allocation. The interleaved allocation allocates banks in units of a basic data width.
The address block based allocation, which allocates a bank for each address block, is effective when an address area which each memory request port accesses is fixed. However, a memory conflict may occur when two or more ports access the same address area. Meanwhile, the interleaved allocation allocates adjacent, successive address values to different banks, and accordingly, the interleaved allocation is effective when accesses to successive addresses of a memory simultaneously occur. For example, when a core accesses four successive bytes as a word, a memory controller causes each bank to access a byte, thereby accessing the four bytes within a clock cycle.